1. Technical Field
The present invention is directed to the field of phase locked loops. More specifically, the invention provides an improved phase locked loop (xe2x80x9cPLLxe2x80x9d) that includes a DC bias circuit. The DC bias circuit enables the PLL to operate using a single supply voltage, and also may be used to eliminate the phase discrimination xe2x80x9cdead zonexe2x80x9d normally associated with the phase detector element of the PLL.
2. Description of the Related Art
Phase locked loops are well-known elements in analog and digital circuit design. A phase locked loop operates by receiving an external reference clock signal and generating a localized oscillator signal that is synchronized with the external reference clock signal. The local oscillator signal may operate at the same frequency as the reference clock signal or at some integer multiple of that frequency. A general description of the theory and operational characteristics of a PLL is contained in Couch, Digital and Analog Communication Systems, Fourth Edition, pp. 289-296.
FIG. 1 is a circuit diagram of a known PLL circuit 10. This circuit 10 includes four primary elementsxe2x80x94a phase detector 14, an operational amplifier 26, a voltage controlled oscillator (VCXO) 32, and a counter 36. This circuit 10 generates a local oscillator signal (PLL clock) 34 that is synchronized with an external reference clock signal 12, but which operates at a higher frequency than the external reference clock 12. This is accomplished by feeding back a divided down version 38 of the local oscillator signal 34 to the phase detector 14, which then compares the phases of the reference clock signal 12 with the feedback signal 38.
The phase detector 14 is preferably a phase frequency detector, and has two inputs and two outputs. The two inputs of the phase detector 14 are coupled to the external reference clock signal 12 and the PLL feedback signal 38, and the two outputs 16A, 16B are coupled to the operational amplifier 26. If the PLL feedback signal 38 leads in phase with respect to the reference clock signal 12, then the phase detector 14 outputs a pulse on the negative phase output (phxe2x88x92) 16A. Similarly, if the reference clock signal 12 leads in phase with respect to the PLL feedback signal 38, then the phase detector 14 outputs a pulse on the positive phase output (ph+) 16B. These output pulses on the positive and negative phase outputs 16A, 16B from the phase detector 14 are characterized by a pulse width that is equivalent to the phase difference between the two inputs.
When the phase difference between the reference clock signal 12 and the PLL feedback signal 38 is nearly zero degrees (i.e., when the PLL is xe2x80x9clockedxe2x80x9d), then the phase detector enters an operational region in which it cannot discriminate the phase difference between the two input signals. This operational region is referred to herein as the xe2x80x9cdead zone.xe2x80x9d As the phase difference of the two inputs approaches zero degrees, the phase detector 14 outputs minimum-width pulses on both the positive and negative phase outputs 16A, 16B.
The phase detector outputs 16A, 16B are coupled to the operational amplifier 26 through a pair of RC circuits. These RC circuits configure the operational amplifier 26 as an integrator. The negative phase output (phxe2x88x92) 16A is coupled to the negative input of the operational amplifier 26 through the RC circuit composed of resistors 18, 28 and capacitor 30. And the positive phase output (ph+) 16B is coupled to the positive input of the operational amplifier 26 through the RC circuit composed of resistors 20, 22 and capacitor 24.
This integrator 18-30 receives the pulses from the phase detector outputs (ph+, phxe2x88x92) 16A, 16B and generates a voltage level at its output that is proportional to the pulse width of the phase pulses. This phase voltage is then provided as an input to the voltage controlled oscillator (VCXO) 32. Because these phase pulses are typically very narrow, particularly when the reference clock signal 12 is very nearly in phase with the PLL feedback signal 38, the voltage output of the operational amplifier is typically near ground. For this reason, the operational amplifier 26 is typically powered using two power supply voltages, such as +/xe2x88x9212 volts or +/xe2x88x9215 volts. This is done because the operational amplifier 26 output becomes non-linear as the output voltage approaches the power supply rails. Thus, it does not operate effectively from a single supply voltage, such as +5V, where the other supply rail is ground, since the phase voltage is typically very close to ground when the PLL is in the locked condition.
The voltage controlled oscillator 32 generates an output clock signal, PLL clock 34, which is characterized by a frequency that is proportional to the phase voltage from the integrator. This clock signal, PLL clock 34, is the localized oscillator signal that is synchronized with the external reference clock 12. The PLL clock signal 34 is then fed back to one of the inputs of the phase detector 14 either directly, or via a counter 36.
The counter 36 is configured as a divide-by-N counter, and it generates the PLL feedback signal 38, which is a frequency divided version of the PLL clock signal 34. By selecting an appropriate value of N, a circuit designer can select the frequency of the PLL clock signal 34 with respect to the external reference clock 12. For example, if the circuit designer desires to generate a synchronized version of the reference clock signal 12, but at a frequency 10 times greater than the reference clock signal 12, then the value of N would be 10.
FIG. 2 is a timing diagram showing the operation of the PLL set forth in FIG. 1. This timing diagram sets forth, from top to bottom, the PLL clock signal 34, the reference clock signal 12, the PLL feedback signal 38, and the corresponding phase pulse signals on the positive and negative phase outputs 16B, 16A of the phase detector 14. As seen in this diagram, during normal operation (i.e., when the PLL is locked), the PLL clock signal 34 is in phase with the reference clock 12, but at a higher frequency. The PLL feedback signal 38 is nearly identical to the external reference clock signal 12 when the circuit is locked, and is in phase with this signal. When locking occurs, the phase difference between the PLL feedback signal 38 and the reference clock signal 12 is very small, and the phase detector 14 enters the xe2x80x9cdead zonexe2x80x9d region in which it cannot further discriminate between the phase difference of the two input signals 12, 38. In this region, the phase detector 14 outputs two extremely narrow pulses at the positive and negative phase outputs 16B, 16A, during the rising edge of the input clocks 12, 38.
The circuit shown in FIG. 1 suffers from two problems. The first problem relates to the dead zone. As described above, at some point during the locking of the PLL, the phase difference between the reference clock signal 12 and the feedback signal 38 becomes so small that the phase detector 14 cannot determine which signal is leading or lagging the other signal. This dead zone region thus presents a minimum threshold phase difference below which the PLL cannot properly lock. Although the characteristics of the phase detector circuitry 14 generally determine the extent of the dead zone region, the minimum threshold difference represented by this region may also be affected by component variations and tolerances in the external RC elements 18-24, 28-30 of the integrator.
The second problem with the circuit shown in FIG. 1 relates to the operational amplifier 26 power scheme. As described above, because the positive and negative phase outputs 16A, 16B of the phase detector 14 are typically very narrow pulses, particularly as the PLL approaches a locked condition, the output voltage of the integrator circuit is typically near zero volts (ground). Because of this very small output voltage, and also because an operational amplifier does not exhibit linear characteristics near its power rails, this requires that the operational amplifier 26 is powered using a plus/minus power supply scheme, such as +/xe2x88x9215 volts. This presents a problem when the apparatus in which the PLL circuit 10 is employed includes only a single power supply, such as +5V.
Therefore, there remains a need in this field for an improved PLL circuit that overcomes the problems noted herein.
A phase locked loop is provided that includes a phase detector, an integrator, a voltage controlled oscillator and a feedback circuit. The phase detector is coupled to a reference clock signal and a feedback signal, and generates positive and negative phase detection signals that correspond to the phase difference between the reference clock signal and the feedback signal. The integrator is coupled to the positive and negative phase detection signals, and converts the positive and negative phase detection signals into an output voltage that is proportional to the phase difference between the reference clock signal and the feedback signal. The voltage controlled oscillator is coupled to the output voltage of the integrator, and generates a local oscillator signal with an oscillation frequency that is proportional to the output voltage of the integrator. The feedback circuit is coupled to the local oscillator signal, and shifts the phase of the local oscillator signal to generate the feedback signal. The phase locked loop locks with a continues phase error between the feedback signal and the reference signal that is substantially equivalent to an integer multiple of the period of the local oscillator signal.